1. Field of the Invention
The present invention relates generally to an SOI substrate and a fabrication process therefor. More specifically, the invention relates to an SOI substrate suitable for a power IC, in which a power element and a control circuit element including an ultra thin film SOI element are integrated on a single chip.
2. Description of the Related Art
When a high-power element having a current path from a surface to a backside surface of a silicon substrate and a control circuit consisting of low tolerance voltage power element are integrated on a single chip, an SOI substrate, in which the control circuit can be formed in an SOI layer isolated from a power element forming region, is employed. This type of SOI substrate has been known from Japanese Unexamined Patent Publication (Kokai) No. Heisei 4-29353 and Proceedings of 1992 ISPSD.
FIGS. 1A to 1F are sections showing steps in sequential order of a fabrication process of the SOI substrate for integrating a vertical type power element and the control circuit, as disclosed in the above-identified Japanese Unexamined Patent Publication No. Heisei 4-29353 (hereinafter referred to as "first prior art").
At first, as shown in FIG. 1A, a patterning is performed for a main surface of a first silicon substrate (N.sup.- type) 1 by way of a photolithographic method, and a shallow step 2 is formed by ion etching or other appropriate methods using a photoresist as a mask.
Then, as shown in FIG. 1B, after forming an insulation layer of SiO.sub.2 by way of thermal oxidation or other appropriate methods, a projecting portion of the insulation layer projecting beyond the main surface of the substrate is removed by polishing, etching or other applicable method so that the exposed surface of the first silicon substrate (N.sup.- type) 1 and the surface of the buried insulation layer 3 lie flush (on the same plane).
Subsequently, as shown in FIG. 1C, the main surface of the first silicon substrate (N.sup.- type) 1, in which the buried insulation layer 3 is formed, is bonded with a main surface of a second silicon substrate (N.sup.+ -type) 4. Then, heat treatment is performed to form a firmly bonded single composite substrate.
Thereafter, the first silicon substrate (N.sup.- type) 1 is ground and polished into a desired thickness. In conjunction therewith, planarization is effected to form an SOI layer 9.
As shown in FIG. 1E, on the planar surface of the SOI layer 9 formed through the planarization, an insulation layer is formed. Then, the insulation layer is patterned by photolithographic method. Using the insulation layer as a mask, alkali-etching is performed to form cross-sectionally triangular isolation grooves 10 for isolating elements.
Thereafter, as shown in FIG. 1F, an insulation layer is formed on the surface of the first silicon substrate (N.sup.- type) 1 by thermal oxidation or other applicable method. Then, by way of CVD method or epitaxial method, a polycrystalline silicon layer is formed. Then, the polycrystalline silicon layer and the insulation layer are polished to form insulation layers 11 on tapered side walls of the isolation grooves 10, and polycrystalline silicon layers 12 buried in the isolation grooves 10. Through the sequence of process set forth above, the SOI substrate, in which the element forming regions are isolated by dielectric body, can be obtained.
FIGS. 2A to 2D are sections showing sequential order of process steps of a fabrication process of an SOI substrate adapted for integrating horizontal-type power elements and control circuit as disclosed in the above-identified Proceedings of 1992 ISPSD (hereinafter referred to as "second prior art").
At first, as shown in FIG. 2A, after forming an insulation layer 103 on one main surface of a first silicon substrate (P.sup.- type) 101 by thermal oxidation, the one main surface is bonded with one main surface of a second silicon substrate (any impurity concentration and conductivity type) 102. Then, heat treatment is performed to form a single composite substrate, in which the first and second silicon substrates are firmly bonded.
Then, as shown in FIG. 2B, the surface of the first silicon substrate (P.sup.- type) 101 is ground and polished into a desired thickness. In conjunction therewith, planarization is performed to obtain the SOI layer 9.
Subsequently, applying the similar processes to those of the steps of FIGS. 1E and 1F, the SOI substrate, in which the element forming regions are isolated by dielectric body, is formed as shown in FIGS. 2c and 2D.
In case of a power IC, in which the high tolerance voltage power element and the control circuit constructed with the low tolerance voltage element are integrated into a single chip, if an ultra thin film SOI element having property of high speed operation, lower power consumption, high reliability and so forth, is integrated, it becomes necessary to completely deplete the SOI layer in order to attain high speed in operation of the ultra thin film SOI element. A thickness of the SOI layer is required in the range of 0.1 .mu.m. The design rule for achieving higher package density associated with reduction of the element dimension always requires a precision of .+-.10% in each dimension, .+-.10% of precision is similarly required for the thickness of the SOI substrate
When the thickness of the SOI layer is set at 0.1 .mu.m for integrating the ultra thin film SOI element in the power IC, in the first prior art, the thickness of the low concentration region of the vertical-type power element forming region (FIG. 1F) becomes thinner simultaneously. In the normal case, the vertical-type power element requires several tens to several hundreds volts of tolerance. For satisfying such tolerance voltage, a thickness of the low concentration region, several to several tens .mu.m is required. Accordingly, in the conventional SOI substrate it has been difficult to form the ultra thin film SOI element for high speed operation and the power element having sufficiently high tolerance voltage, on the common substrate.
Similarly, the horizontal type power element is also required the tolerance voltage of several tens to several hundreds volts. Thus, approximately 1 .mu.m of thickness becomes required for the SOI layer in the region for forming such power elements. However, in the SOI substrate of the second prior art, the SOI layer in the horizontal-type power element forming region should have a thickness of approximately 0.1 .mu.m similarly to the ultra thin film SOI layer. Therefore, it is not possible to form the ultra thin film SOI element operable to high speed and the horizontal-type power element having sufficient high tolerance voltage on the common substrates.
Also, in the second prior art, the thickness of the horizontal-type power element forming region (FIG. 2D) becomes 0.1 .mu.m. Therefore, the power element with sufficient performance cannot be fabricated in the conventional fabrication process.